Bipolar junction transistors (BJTs) are key parts of analog integrated circuits. BJTs can be grouped as NPN BJTs (NBJTs) and PNP BJTs (PBJTs). A symbol for an NPN BJT, which comprises a collector C, a base B, and an emitter E, is shown in FIG. 1A. There are two types of commonly designed BJTs using conventional CMOS technology. FIGS. 1B and 1C illustrate a vertical-BJT, wherein a top view is shown in FIG. 1B and a cross-sectional view is shown in FIG. 1C. The vertical-BJT is an NPN transistor comprising doped regions, namely an emitter E, a base B and a collector C. To enhance emitter injection efficiency, the emitter E is enclosed by the base contact B and the collector C. The emitter E and the base contact B are formed in a P-well and the collector C is formed in an N-well, wherein the P-well and the N-well are further formed on a deep N-well (DNW). Since the base regions include the P-well and the base contact B, the emitter/base junction and the collector/base junction are formed between vertically located components, and the respective BJT is referred to as a vertical BJT.
FIGS. 1D and 1E illustrate a (NPN) lateral-BJT. Again, a top view is shown in FIG. 1D and a cross-sectional view is shown in FIG. 1E. Since the P-well, which is part of the base region, has a portion inserted between the emitter E and the collector C, the emitter/base junction and the collector/base junction are formed between laterally located components, and the respective BJT is referred to as a lateral-BJT (LBJT).
The ability for improving the gain of conventional vertical-BJTs and lateral-BJTs is limited for the following reasons. Using FIG. 1E as an example, besides the intentionally formed BJT, there is also a parasitic transistor NBJT, whose collector, base and emitter are formed by the region E, the P-well and the deep N-well (DNW), respectively. Since a significant portion of the emitter/base junction of the parasitic transistor NBJT is located at a surface 2, which is located at the bottom of the emitter E, to reduce the effect of the parasitic transistor NBJT, it is preferred that the surface 2 has a small area. On the other hand, in order to improve the emitter injection efficiency of the lateral-BJT, it is preferred that the path between the emitter E and collector C, which is symbolized by arrows 4, has a large area. This requires the length LE of the emitter E and collector C to have a great value. Great length LE and small area of the emitter E are conflicting requirements, which means that the improvement of the lateral-BJT comes with the cost of greater parasitic BJT. A dilemma for conventional vertical-BJTs is that the base width, which is substantially equal to a depth of the P-well as shown in FIG. 1C, is not scalable, if the vertical-BJTs are formed using a same technology as the formation of CMOS devices.
Conventionally, the BJTs are formed using conventional CMOS technology, and are typically formed simultaneously with the formation of CMOS devices. This incurs drawbacks. CMOS devices often have pocket implants, and thus the same pocket implants are performed on BJTs. The pocket implants result in the increase in the dosage in the base regions, hence decrease in current gain. Furthermore, the lightly-doped source/drain (LDD) implants causes sharp dose profile at base/collector junctions, resulting in lower breakdown voltages.
Therefore, there is the need for improving the gain of lateral-BJTs, the scalability of the respective base widths, and the emitter injection efficiency, without the cost of an increase in parasitic effects.